The present invention relates to large bandwidth high frequency amplifiers to be placed in the receiver section of a high speed transmission system and more particularly to an improved differential amplifier provided with a parallel feedback loop to amplify high frequency signals wherein the DC offset is significantly reduced and the input impedance matching improved.
In the receiving part of high speed wired transmission systems (like Ethernet), there is a need for the amplification of high frequency low power signals. This is achieved with a dedicated differential amplifier basically consisting of a chain of low gain large bandwidth amplifiers with a parallel feedback loop, usually called post-amplifier or PA, that is placed after the optical circuitry (photodiode and associated transimpedance circuit) of the receiving section.
The block diagram of such a conventional amplifier is shown in FIG. 1. Now turning to FIG. 1, the conventional differential amplifier referenced 10 is comprised of an input matching circuit 11, an amplification section 12 consisting of a chain of large bandwidth amplifiers to obtain enough gain in the frequencies of interest (in the GHz range) and finally a circuit block 13 in the DC feedback loop connected in parallel between the inputs and outputs of said amplification section 12. All these circuit components are mounted in a differential manner. As apparent in FIG. 1, input matching circuit 11 consists of a single resistor for the sake of simplicity, that is mounted in parallel between two input terminals 14 and 15 receiving single-ended input signals INp and INn respectively from a preceding stage schematically represented by a voltage supply Vin and a resistor R. Vin will be referred to hereinbelow as the input voltage for the sake of simplicity. Corresponding single-ended output signals OUTp and OUTn are available at output terminals 18 and 19 respectively, and likewise define the output signal Vout, such as Vout=VOUTp−VOUTn. Feedback block 13 includes an amplifier 16 (for further amplification of the output signal Vout) and a RC network 17 comprised of blocks 17′ for low pass filtering and 17″ to perform the summation of the direct input and feedback signals at nodes A and B at the inputs of the first amplifier of amplification section 12 as shown in the drawing. The dotting which is made at nodes A and B allows the desired reduction of the DC offset by the single-ended feedback signals Fbn and Fbp. As known for the skilled professional, the voltage V at the inputs of the amplification section 12 is a function of Vin and Vfb, where Vfb=VFBp−VFBn. Note that a quite similar circuit is described in the article: “622 Mb/s CMOS limiting amplifier with 40 dB dynamic range” by T. Yoon & B. Jalali, published in Electronics Letters, Sep. 26, 1999, Vol. 32 No 20, pp 1920-1921.
The conventional differential amplifier shown in FIG. 1 only partially reduces the DC offset, because, unfortunately, it amplifies not only the useful input signal but also any DC offset signal, coming from the previous circuits or internally generated at the input terminals of amplifier 10. The amplitude of this DC offset signal can be of the same order of magnitude or even greater than the one of the input signal itself and then can detrimentally saturate the differential output signal Vout with invalid information. In addition, the feedback block 13, which connect the RC network 17 in parallel on the input matching circuit 11 significantly degrades the input impedance matching, referred to as the scattering parameter S11 in the technical literature.